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Software Defined Radio on Zynq®-7000 All Programmable SoC

This course combines the high-speed analog signal chain from RF to baseband with FPGA-based digital signal processing for wireless communications. Topics include the high-speed analog signal chain, direct conversion radio architecture, the high-speed data converter interface and FPGA-based digital signal processing for software defined radio. Attendees will work with the latest generation Analog Devices high-speed data converters, RF and clocking devices, along with the Xilinx Zynq®-7000 All Programmable SoC. Hands-on labs featuring Xilinx DSP design tools and IP, including MathWorks’ Simulink® model-based design, will introduce attendees to system-level concepts that are both powerful and intuitive.
Prerequisite:

  • Completion of the Introduction to Zynq-7000 All Programmable SoC SpeedWay or equivalent
  • Familiarity with MathWorks MATLAB® and Simulink® (recommended, not required)

Table of Contents

Chapter-1 Zynq SDR Speedway Introduction View
Chapter-2 Zynq SDR Speedway Part 1 View
Chapter-3 Zynq SDR Speedway Part 2 View