Sorry, you need to enable JavaScript to visit this website.

Vivado - IP core instantiated in VHDL

Zedboard forums is currently read-only while it under goes maintenance.

Unsolved
3 posts / 0 new
MartinGaraj
Junior(1)
Vivado - IP core instantiated in VHDL

Is there a way to use IP cores directly in code (VHDL/Verilog) instead of placing them into Block Design (graphical user interface) ?
 
May I ask for an example with Floating Point Operator (in VHDL/Verilog) ? How to initialize it (settings of the core) ? (because the IP core can be set to provide different operations)
 
 
The reason:
- compact code (without the need to switch between code and graphical user interface / Block Design)
- less work
- Block Design is utilized just for top view

JFoster
Moderator(76)
Hello MartinGaraj, 

Hello MartinGaraj, 

Firstly we recommend using the UltraFlow Design Methodology which utilize the Block Design graphical user interface. Please refer to the below reference.

http://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-desi...

As for your reasons for wanting to move to away from the Block Design

---It won't nessecarily be more compact unless you plan on using custom code (see reference above)

---It would be faster and easier to use Vivado Block Diagram GUI

---One other thing of note is that the Block Design is not for top view only. It provides you with a hierarchial view that you can dig down through.

If you still want to do everything directly in code (No Block Design GUI) you can still do so. This is done by opening your IP Catalog, double clicking on the IP you wish to use, this then allows you to customize your IP before you generate it. Once you click ok and generate the IP it will appear in your project folder where you will have access to the HDL code. I would also suggest  you keep a copy of the project just in case you end up needing to change your IP.

Also if you look in the C:\Xilinx\Vivado<version number>\data\ip directory you can find all the RAW IP.

--Josh

 

 

johnabel
Junior(0)
Yes, there is, at least in

Yes, there is, at least in Vivado 2017.2:
- Open the IP catalog from Flow Navigator
- Choose the IP you want to include in your VHDL/ Verilog and double click
- In the pop up asking whether to add it to a block design, or customize it and add it as RTL, select this last option
- Customize the module and click OK, this should also generate the products and the IP should apper in the Design Sources hierarchy
- In Design Sources, highlight the IP and in Source File Properties, copy the path where it is
- Open that folder and open the file ending with vho, there you will find enclosed in comments, both the declaration and instantiation templates, copy them and paste in your file. Remember to replace the signals to what the instance is connected to (not the ones in the declaration)