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CDMA source/dest address: lab4 in workshop -- Advanced Embedded System Design on Zynq using Vivado

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jge
Junior(0)
CDMA source/dest address: lab4 in workshop -- Advanced Embedded System Design on Zynq using Vivado

Hello,
 
I'm trying to understand how the address setup works in the Lab4 of the workshop 2017: 
https://www.xilinx.com/support/university/vivado/vivado-workshops/Vivado-adv-embedded-design-zynq.html
 
 
It seems 'working' but the way it setup the transfer source/destination address is little confusing:
 

#define PROCESSOR_BRAM_MEMORY 0x80000000 // BRAM Port A mapped through 1st BRAM Controller accessed by CPU
#define CDMA_BRAM_MEMORY 0xC0000000 // BRAM Port B mapped through 2nd BRAM Controller accessed by CDMA
#define DDR_MEMORY 0x01000000
let's say the option 1 selected as "  "
 
 

case '1' :
// case '2' :
source = (u8 *)PROCESSOR_BRAM_MEMORY;
cdma_memory_source = (u8 *)CDMA_BRAM_MEMORY;
destination = (u8 *)DDR_MEMORY;
cdma_memory_destination = (u8 *)DDR_MEMORY;
print("BRAM to DDR transfer\r\n");
break;
the 'source' and 'destination' buffer initilized (cleared destination after non-DMA trial) as :
 
 

// Initialize src memory
for (i=0; i<numofbytes; i++)
*(source+i) = numofbytes-i;

// clear destination memory
for (i=0; i<numofbytes; i++)
*(destination+i) = 0;
 after started a polling mode DMA transfer: note with src/dest as "cdma_memory_source/cdma_memory_destination ", NOT "sourc e/destination" already setup, 
 
the 'destination' buffer is compared against the 'source'  to see 'match' or not; if match then DMA succeeded -- WHY? (unless 'source' and 'cdma_memory_source the same; and "destination" and "cdma_memory_destnation" the same too)
 

// DMA in polling mode
XAxiCdma_IntrDisable(&xcdma, XAXICDMA_XR_IRQ_ALL_MASK);
print("Starting transfer through DMA in poll mode\r\n");
// reset timer
XScuTimer_RestartTimer(TimerInstancePtr);
Status = XAxiCdma_SimpleTransfer(&xcdma, (u32) cdma_memory_source, (u32) cdma_memory_destination, numofbytes, NULL, NULL);

if (Status != XST_SUCCESS) {
CDMA_Status = XAxiCdma_GetError(&xcdma);
if (CDMA_Status != 0x0) {
XAxiCdma_Reset(&xcdma);
xil_printf("Error Code = %x\r\n",CDMA_Status);
}
return XST_FAILURE;
}

while (XAxiCdma_IsBusy(&xcdma)); // Wait
CntValue1 = XScuTimer_GetCounterValue(TimerInstancePtr);

CDMA_Status = XAxiCdma_GetError(&xcdma);
if (CDMA_Status != 0x0) {
XAxiCdma_Reset(&xcdma);
xil_printf("Error Code = %x\r\n",CDMA_Status);
}
else {
xil_printf("Moving %d bytes through DMA in poll mode took %d clock cycles\r\n", numofbytes, TIMER_LOAD_VALUE-CntValue1);
print("Transfer complete\r\n");
polled_cycles = TIMER_LOAD_VALUE-CntValue1;
Error = 0; // reset for interrupt mode transfer
}

for (i = 0; i < numofbytes; i++) {
if ( destination[i] != source[i]) {
xil_printf("Data match failed at = %d, source data = %x, destination data = %x\n\r",i,source[i],destination[i]);
break;
}
}
print("Transfered data verified\r\n");
 
note: the "destination" and "cdma_memory_destination" actually point to the same block (0x0100 0000) . The transfer  is a 'success'.
BUT the "source" and "cdma_memory_source" pointed to different blocks. Although the "destination" block indeed resulted in the same as "source", but contents of  the "cdma_memory_source" (starting from address 0xC000 0000) shown as "?" in debug mode. 
How does the CDMA transfer get the data from 'source; instead of 'cdma_memory_source"? , or 
the memory block starting from 0xC000 0000 is not 'visible' in SDK debug mode???
 
 
 

JFoster
Moderator(76)
Hello,

Hello,

Please ask this question over at the Xilinx forum as it is in regards to their training.

Thanks!

Josh